A logic circuit is a circuit designed to perform a particular logical function based on the concepts of "and", "either-or", "neither-nor", etc. Normally, these circuits operate between two discreet voltage levels, i.e. high and low logic levels, and are described as binary logic circuits.
Binary logic circuits are the basic building blocks of data processing systems and almost any electronic computing device. Binary logic circuits are extensively used in computers to carry out instructions and arithmetical processes. Any logical procedure may be effected by using a suitable combination of these basic gates.
Because of their low power dissipation, complementary CMOS (metal-insulator-semiconductor) field-effect transistors (FETs) are often used to construct such logic circuits.
Because logic circuits are often cascaded in a plurality of connected stages, clock pulses are applied to the elements of a logic circuit to effect logical operations, i.e., drive the logical circuit. Referring to FIG. 1, there is illustrated typical logic circuit 10, which may implement any logical function, having Data In inputs A--Z and a Data Out output. A clock signal is inputted to logic circuit 10 in order to drive the Data In inputs through logic circuit 10 in order to effect the associated logical function implemented in logic circuit 10 upon the data inputs in order to arrive at the solution, which is outputted as Data Out.
The periodic clock signal also serves to prepare, or precharge, logic circuit 10 so that it is ready for the next series of Data In inputs subsequent to outputting the previous Data Out.
One problem with utilizing a clock signal to synchronize all logical operations within very large scale integrated (VLSI) circuitry is that the overall system clock signal may be subjected to noise and clock skew while being transmitted throughout the VLSI circuitry, resulting in a distorted and inaccurate clock signal incorrectly driving any particular logic circuit 10, which may ultimately result in inaccurate operation of the VLSI circuitry, which could be a portion of a central processing unit ("CPU"). Also, the clock speed is determined by the slowest path in the CPU. Another problem is that traditional clocking for precharged circuits also requires the intersection of a "precharge phase" or "time" into the system. This time may decrease the overall system performance by requiring foot devices (also known as evaluate or interrupt devices) causing an increase in power and delay.
Referring to FIG. 2, a solution to the foregoing problem is the use of reset circuit 20 in order to precharge logic circuit 21 to a ready state so that it can accept the Data In and perform the logical operation correctly. In such a design, a clock signal is not needed.
Referring next to FIG. 3, there is illustrated a cascade of logic circuits 1, 2, 3, . . . N. The output Data Out is sent to reset circuit 20, which operates to reset each of logic circuits 1-N. Timing circuits 31, 32, 33 and 34 operate to properly time the resetting of the logic circuits 1-N so that the reset occurs at the proper time, e.g., after each logic circuit has performed its operation and outputted its result. Timing circuits 31-34 may comprise conventional buffer circuits.
A more detailed diagram of a self-resetting logical circuit is illustrated in FIG. 4, wherein there is illustrated typical logic circuit 40, which is operable to perform a logical AND operation on the input data Din1 and Din2. The circuit, being made in the CMOS technology, has its P-channel FETs indicated by a rectangle with a diagonal line formed therein and a gate electrode arranged adjacent thereto and its N-channel FETs indicated by a rectangle without a diagonal line and a gate electrode arranged adjacent thereto. This convention will be followed through the various FIGURES. N-FETs 41 and 42 receive the inputted data. If either Din1 or Din2 is at a logical low level, then node 45 is at a logical high level resulting in a logical low level outputted as Data Out because of the transmission of the high level at node 45 through inverter circuit 43. If both of the inputs Din1 and Din2 are at a logical high level, then N-FETs 41 and 42 will be turned on resulting in a logical low level at node 45 resulting in a logical high level being outputted at Data Out.
Logical circuit 40 also includes P-FET device 44 coupled between node 45 and voltage supply VDD. Reset circuit 20 is coupled between the output terminal and the gate electrode of device 44. As will be described below, reset circuit 20 may act to apply a low level signal to the gate electrode of 44 upon receiving the high level output from the output of inverter circuit 43. Thus, upon output of a high level signal from circuit 40, reset circuit 20 will result in a precharging of node 45 to a high level through the switching on of P-FET device 44. Circuit 40 is then ready to receive another set of input values for a subsequent logical operation.
Referring next to FIG. 5, there is illustrated one possible embodiment of reset circuit 20 wherein Data Out is received at the gate electrode of N-FET device 50, which turns on to pull node 51 to a ground, or low voltage, potential, which is sent as the Reset signal to device 44 in FIG. 4.
Referring next to FIG. 6, there is illustrated another embodiment of reset circuit 20 whereby the Data Out signal is received at the gate electrode of N-FET device 61, which pulls node 64 to a ground potential, which is outputted as the Reset signal. The Reset signal is also supplied to delay circuit 63, which may comprise one or more buffer circuits, which supplies the delayed Reset signal to the gate electrode of P-FET device 62, which operates to pull node 64 back to a high potential for the next Data Out signal to be received by reset circuit 20.
It is clear that circuit 40 may not be properly reset by reset circuit 20 if the logical level of Data Out is low, since reset signal 20 may convert this outputted logical low level to a high level, which will not turn on P-FET 44. Thus, unless the ground potential is applied to node 45 by the input data applied to the gate electrodes of N-FET devices 41 and 42, circuit 40 may not be properly reset, or precharged, for a subsequent logical operation.
Referring to FIG. 8, there is illustrated a block diagram of a solution to the foregoing problem whereby logic circuit(s) 90 (described in more detail below with respect to FIG. 9) receives a complementary value (inverse) for each data input and outputs a complimentary Data Out (i.e., inverse of Data Out) along with the true Data Out. This is known as a logic circuit having dual-rail inputs and outputs. Both of these outputs are then applied to reset circuit 70, which resets logic circuit(s) 80 through timing circuitry 81.
Referring to FIG. 7, there is shown an implementation of reset circuit 70 whereby Data Out and the complement of Data Out are received by N-FET devices 71 and 72, respectively, arranged in parallel between node 73 and the ground potential. With this arrangement, regardless of the level of Data Out, a proper reset signal will be applied to the logic circuit, i.e., a low level signal will be applied to the gate electrode of P-FET device 44 for circuit 40. Note, reset circuit 70 also utilizes its own precharging circuitry through the use of delay circuit 63 and P-FET device 62 in a similar manner as described above with respect to FIG. 6 in order to reset a high voltage level at node 73 for subsequent reset operations.
In order to implement logic circuitry having both Data Out and the complement of Data Out, additional circuitry must be implemented within each logic circuit, such as illustrated in FIG. 9. FIG. 9 illustrates logic circuit 90, which comprises logic circuit 40 and its complement, logic circuit 91. Logic circuit 91 is similar to logic circuit 40 except that it receives the complements of Din1 and Din2 into N-FET devices 93 and 94, respectively, resulting in the output of a complement to Data Out. Both the output Data Out and the complement of Data Out are inputted into reset circuit 70, which sends a reset signal to P-FET devices 44 and 96 in order to precharge logic circuits 40 and 91, respectively. Since reset circuit 70 is tied to both the output and the complement of the output of circuit 90, reset circuit 70 will be able to send a low level reset signal to devices 44 and 96 in order to precharge both of logic circuits 40 and 91, respectively.
The disadvantage of circuit 90 is that it requires essentially double the circuitry for each logic circuit 90 in order to appropriately implement the reset functionality. Within VLSI circuitry, doubling the area requirement for each logic circuit will basically result in double the area required for the VLSI circuitry, which may not be desirous.
Thus, there is a need in the art for an implementation of reset functionality within logic circuitry that does not require dual-rail inputs and outputs for each logic circuit.